High performance integrated circuits often require metal oxide semiconductor (MOS) transistors to operate at different voltages. Given the electric field constraints required for reliable transistor operation, different operating voltages will require that the MOS transistors on the same integrated circuit be formed with more than one gate dielectric thickness. For example a 0.18 μm gate length transistor designed to operate at 1.8 volts may require a gate dielectric thickness of 38 Å while a 0.5 μm gate length transistor designed to operate at 3.3 volts will require a gate dielectric thickness of 65 Å.
Shown in FIG. 1 are two MOS transistors 120 and 130 with differing gate dielectric thickness. The semiconductor substrate 10 can comprise epitaxial layers and/or buried insulator structures. The isolation structure 20 is a shallow trench isolation (STI) structure and is formed using standard processing technology. Other isolation structures such as localized oxidation of silicon (LOCOS) can also be used. To form the gate dielectric layers 140 and 150 a split gate process can be used. In the split gate process a first dielectric layer is grown on the surface of the semiconductor substrate 10. The region of the first dielectric layer that will eventually form the dielectric layer 150 is masked using a patterned photomask and the unmasked regions of the first dielectric layer removed. Following the removal of the patterned photomask the dielectric layer 140 is formed. Formation of dielectric layer 140 comprises thermally growing the dielectric layer. During the growth process addition dielectric layer thickness is added to the remaining first dielectric layer resulting in dielectric layer 150 being formed. For the transistors described above the dielectric layer 140 for the lower voltage transistor 120 will be about 38 A thick and the dielectric layer 150 for the higher voltage transistor 130 will be about 65 A thick. Following the formation of the dielectric layers 140 and 150, the gate structures 60 and 70 of the MOS transistors are formed. If source and drain extension regions are required these are formed at this time by implanting the required dopant species into the semiconductor substrate aligned to the edge of the gate structures 60 and 70. Sidewall structures 80 and 90 are formed adjacent to the gate structures 60 and 70 followed by the formation of the source and drain regions 100 and 110.
As the current size of the MOS transistors is reduced the thickness of the gate dielectric layers used to form these transistors must also be reduced to ensure proper operation. The transistor gate leakage current is related to the thickness of the dielectric layer increasing with a reduction in dielectric layer thickness. For the thinner gate dielectric layer (i.e., 140 in FIG. 1) techniques such as the addition of nitrogen to the dielectric layer have been used to reduce the transistor gate leakage current. Previously the thickness of the dielectric layer for the higher voltage transistor has been such that no special techniques were required to keep the gate leakage current for these transistors below acceptable levels. However as the transistors continue to scale downwards gate leakage currents from the higher voltage transistors 130 with the thicker dielectric layers 150 is becoming a serious limitation to integrated circuit performance. There is therefore a need for a method to simultaneously optimize both dielectric layers for reduced gate leakage current while reducing the dielectric layer thickness.